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chipsalliance

chipsalliance/Surelog

C++Apache-2.0active
88Health

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Stars466
Forks86
Open Issues47
Contributors86
Last Push0d ago

Health Breakdown

Activity
25
Community
25
Maintenance
13
Popularity
25
#antlr#antlr4-grammar#elaboration#linter#parser#parser-ast#preprocessor#python-api#systemverilog#uvm#verilog#vpi#vpi-api#vpi-standard
View on GitHub ↗Issues (47) ↗Pull Requests ↗Wiki ↗

Should you contribute to chipsalliance/Surelog?

chipsalliance/Surelog has a FoundDev health score of 88/100, which puts it in the active-and-maintained tier. The maintainer team is shipping recently, issues are being closed, and a PR you open this week has a realistic chance of being reviewed.

Last push was 0 days ago — that signals an actively maintained project. New issues are likely to get a maintainer response within days. The project is written primarily in C++, so prior C++ experience will shorten ramp-up.

Licensed under Apache-2.0, a standard OSI-approved license — safe to contribute to under normal employer IP policies.

Community

chipsalliance88

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

active
46686 contributors47 issues
0d ago

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